Field of the Disclosure
Embodiments of the present disclosure generally relate to an improved method and system for error correction in non-volatile memory cells.
Description of the Related Art
The performance of non-volatile memory (NVM) is limited by the raw bit error rate of NVM cells. Phase change memory (PCM) is a type of non-volatile memory in which reading occurs much faster than writing. The write noise may introduce errors, such that the actual bit-value stored in the NVM is not what was intended. For example, an intended bit-value of 0 might be inadvertently flipped to an incorrect bit-value of 1. Correcting write errors is essential in increasing the lifetime and in assuring the data integrity of NVM cells.
Various conventional error correction schemes are available to address such write errors. Oftentimes error correction codes (ECCs), for example BCH codes, are used to detect and correct write errors. However, conventional error correction codes result in decreased data rate and increased read latency because of the decoding complexity involved.
Therefore, there is a need in the art for an improved method and system for error correction in non-volatile memory cells.